Solid-state power controllers (“SSPC”) have been designed to have a current channel that can be used individually or combined with current channels of other SSPCs to achieve a desired current capacity. However when paralleling, the individual channels may experience different conditions such as, for example, in the event that outrush current demands vary or component values including board parasitics vary to a sufficient degree to create a current imbalance or wiring resistance varies from channel to channel. Some channels may become overloaded while other channels may remain within operating specifications. In some instances, this results in possible overloading of one or more circuits, trip coordination complexity, and other factors, such as thermal “hot spots.”
Conventional SSPC systems designs have attempted to balance the current flowing through the SSPC channels by matching field effect transistor (“FET”) values and/or matching trace line lengths to naturally approximately balance in the current loading between channels.